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Ordering number:ENN3411B
CMOS IC
LC8953
General-Purpose 68000 MPU Peripheral Interface IC
PUPPET (Programmable Universal Peripheral/Port Expansion uniT) Overview
There are many application systems using the 68000 chip as their MPU (Main Processing Unit). It is common to them that designing the peripheral circuits such as address decoders, interrupt controllers, serial interface and DMA (Direct Memory Access) has become a time-consuming task. As a result, each of the application systems requires a larger board size, which makes it very expensive. In addition, 68000 family peripherals are highly advanced functional ICs. The application system designer finds it difficult to use them in small- and medium-sized application products in terms of cost as well as functional complexity. The LC8953 (Programmable Universal Peripheral/Port Expansion uniT) has optimized on-chip control circuits enabling the 68000 MPU to control the LC8951 (RCHIP) and LC8955. Use of the optimized control circuits allows the user to easily build up CD-ROM and CD-I systems which offer excellent performance in terms of space and cost.
Package Dimensions
unit:mm 3153A-QIP160E
[LC8953]
1.6 1.325 0.65 120 31.2 28.0 0.3 81 80 1.325 0.15
31.2 28.0 0.65
1.325
121
41 160 1.6 1.325 1 40 3.56max 0.8 0.1 3.2 29.5
0.8
SANYO : QIP160E
Features
* Programmable address decoder. * Programmable DTACK generator. * Programmable interrupt handler. * Clock divider. * Bus error generator. * TICK generator (programmable timer interrupt generator) * Serial mouse interface (1 port) * LC8951 (RCHIP-Real-time error Correction & Host-interface Integrated Processor) interface. * LC8955 interface. * Micro-programmable 1-channel DMA controller.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
80101TN (KT)/D1394TH (ID)/N010JNKI No.3411-1/9
LC8953
Block Diagram
No.3411-2/9
LC8953
Pin Assignment
No.3411-3/9
LC8953
Pin Functions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Name1 VSS DATAEMP UNDFLOW BUFFULL BUSY XAPWR XAPRD XAPCS SA0 SA1 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 XAPDTEN VDD VSS XREAD TEST HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HDE XSTEN XDTEN DRQWAIT XCMD XHRD XHWR CDPORT0 VDD VSS CDPORT1 CDPORT2 XAPTFR XIORD XIOWR XCUSRIO XCIO0 XCIO1 XCIO2 XCIO3 XCIO4 XCIO5 XCIO6 XCIO7 XCEXT0 XCEXT1 XCNVRAM XCVSC I/O - I I I I I I I O O I/O I/O I/O I/O I/O I/O I/O I/O O - - I I I/O I/O I/O I/O I/O I/O I/O I/O I I I I O O O I/O - - I/O I/O I O O O O O O O O O O O O O O O External address select signal output pins NVRAM address select signal output pin VSC address select signal output pin Programmable I/O address select signal output pins Erasure flag signal input pin for the LC8951 (RCHIP) Status enable signal input pin for the LC8951 (RCHIP) Data enable signal input pin for the LC8951 (RCHIP) Data request/Wait select signal input pin for the LC8951 (RCHIP) Command/Data select signal output pin for the LC8951 (RCHIP) Data read signal output pin for the LC8951 (RCHIP) Data write signal output pin for the LC8951 (RCHIP) General-purpose input/output signal pin +5V supply pin Ground pin General-purpose input/output signal pins Mask operation select signal input pin for the LC8955 automatic request transfer IC read signal output pin for Intel peripheral ICs Write signal output pin for Intel peripheral ICs User I/O address select signal output pin Data signal I/O pins for the LC8951 (RCHIP) Data enable signal output pin for the LC8955 for automatic request transfer +5V supply pin Ground pin Read signal input pin for the LC8955 for automatic request transfer Test input pin (Tied low) Data signal I/O pins for the LC8955 Ground pin Data empty signal input pin for the LC8955 Underflow signal input pin for the LC8955 Buffer full signal input pin for the LC8955 Busy signal input pin for the LC8955 Data write signal input pin for the LC8955 Data read signal input pin for the LC8955 Chip select input pin for the LC8955 Resister select signal output pins for the LC8955 Function
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No.3411-4/9
LC8953
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Number 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 Name1 VDD VSS XCROM0 XCROM1 XCROM2 XCROM3 ROMMOD1 ROMMOD0 XDTACK XRW XLDS XUDS XAS D0 D1 D2 D3 D4 D5 D6 D7 VSS D8 D9 D10 D11 D12 D13 D14 D15 VDD A23 A22 A21 A20 A19 A18 A17 A16 VSS A15 A14 A13 A12 A11 A10 A9 VDD A8 A7 A6 A5 A4 A3 A2 A1 VSS XIPL2 XIPL1 XIPL0 I/O - - O O O O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I/O - O O O Interrupt level signal output pins for the MPU Ground pin Address bus signal input/output pins +5V supply pin Address bus signal input/output pins Ground pin Address bus signal input/output pins +5V supply pin Data bus signal input/output pins Ground pin Data bus signal input/output pins ROM mode select signal input pins Data acknowledge signal input/output pin Read/Write signal input/output pin Low-order data strobe signal input/output pin High-order data strobe signal input/output pin Address strobe signal input/output pin ROM address select signal output pins +5V supply pin Ground pin Function
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LC8953
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Number 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Name1 VDD FC0 FC1 FC2 XBERR XRESET XHALT CPUCLK XDBDIR XBR XBG XBGACK XOWN XEXTDMA1 XEXTDMA0 XEXTBGAK XCS CLKSEL XSWAP ORGCLK VDD VSS TICKCLK XIACKALL XIACK5 XIACK4 XIACK3 XIACK2 XIACK1 XIACK0 XIRQ5 XIRQ4 XIRQ3 XIRQ2 XIRQ1 XIRQ0 RXD APSEL0 APSEL1 APSEL2 VDD I/O - I/O I/O I/O O I I O O O I O O I/O I/O I I I I I - - I O O O O O O O I I I I I I I O O O - +5V supply pin General-purpose output port pins Mouse data signal input pin Interrupt request signal input pins Interrupt acknowledge signal output pins Bus error signal output pin Reset signal input pin Halt signal input pin MPU clock signal output pin Data bus direction signal output pin DMA bus request signal output pin DMA bus request-granted signal input pin DMA bus request-granted acknowledge signal output pin DMA cycle active signal output pin DMA signal input/output pins External DMA bus request-granted acknowledge signal input pin Address decoder mode select signal input pin Master clock (CPUCLK) divider select signal input pin Memory swap function select signal input pin Clock input pin +5V supply pin Ground pin External clock input pin for the tick generator Interrupt acknowledge common signal output pin MPU function code signal input/output pins +5V supply pin Function
1. An "X" at the beginning of a pin name indicates negative logic.
No.3411-6/9
LC8953 Specifications
Absolute Maximum Ratings at VSS = 0V
Parameter Maximum supply voltage Input and output voltage Allowable power dissipation Operating temperature range Storage temperature range Soldering temperature Symbol VDD max VI, VO Pd max Topr Tstg Tsol Manual soldering, 3s Reflow soldering, 10s Ta=25C Ta=25C Ta70C Conditions Ratings - 0.3 to +7.0 - 0.3 to VDD +0.3 400 - 30 to +70 - 55 to +125 350 235 Unit V V mW C C C C
Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0V
Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions Ratings min 4.5 0 typ 5.0 max 5.5 VDD Unit V V
DC Electrical Characteristics at Ta = -30 to +70C, VSS = 0V, VDD = 4.5 to 5.5V
Parameter Input high-level voltage Input low-evel voltage Input high-level voltage Input low-level voltage Output high-level voltage Outpu low-level voltage Input leakage current Output leakage current Input high-level voltage Input low-level voltage Output high-level voltage Outpu low-level voltage Symbol VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 IL IOZ VIH3 VIL3 VOH2 VOL2 Conditions TTL compatible: All input pins (including bidirectional pins) except those listed in notes 1 and 2. TTL-compatible Schmitt: See note 1. IOH=- 3mA IOL=3mA VI=VSS, VDD High-impedance output All input pins except those listed in note 3. All bidirectional pins Ratings min 2.2 0.8 2.5 0.6 2.4 0.4 - 25 - 100 0.7VDD 0.3VDD 2.4 0.4 +25 +100 typ max Unit V V V V V V A A V V V V
CMOS compatible: ORGCLK (pin 139) IOH=- 6mA IOL=6mA XDTACK (pin 68), D0 to D15 (pins 73 to 89)
Notes 1. DATAEMP (pin 2), UNDFLOW (pin 3), BUFFULL (pin 4), BUSY (pin 5), XSTEN (pin 33), XDTEN (pin 34), DRQWAIT (pin 35), XAPTFR (pin 44), XRESET (pin 125), XHALT (pin 126), XEXTBGAK (pin 135), XIRQ0 to 5 (pins 150 to 155), RXD (pin 156) 2. ORGCLK (pin 139) 3. XDTACK (pin 68), D0 to D15 (pins 73 to 89)
No.3411-7/9
LC8953
Internal Functional Blocks The PUPPET consists of about 10 functional blocks. See the "Block Diagram". PADEC (Programmable Address Decoder) The PADEC functional block is used to generate the chip select (CS) signals for ROM, RAM, I/O devices and so on. The CS signal addresses are programmable, which enables address allocation specific to your system configuration. DTAKGEN (Programmable DTACK Generator) The DTAKGEN functional block is used to generate the data acknowledge signals for the chip select address space selected by the PADEC. The access speed of peripheral IC devices is generally slower than that of the main processing unit (MPU). To adjust this speed gap between them, the user is allowed to insert from 0 to 4 wait cycles into each address cycle. The number of wait cycles to be inserted is programmable. In addition, the user is permitted to disable the DTACK (active low) generator so that it can be generated by an external device. PINTH (Programmable Interrupt Handler) The PINTH functional block is used as an interrupt handler to output the vectored numbers corresponding to the 68000 MPU vectored interrupts. Each of the IPL levels and vectored numbers for internal block/external interrupt requests is programmable. RCHIPIF (LC8951 RCHIP Interface) The RCHIPIF functional block is used to provide the interface between the 68000 MPU and the LC8951 RCHIP. This interface enables direct communication between them. As a result, status data, data signal and error bit information can be directly communicated between them. ADPCMIF (LC8955 Interface) The ADPCMIF functional block is used to provide the interface between the 68000 MPU and the LC8955. This interface enables direct communication between them. As a result, data can be directly read from or written to internal registers of the LC8955 from the MPU. TICKGEN (Tick Generator) The TICKGEN functional block is used to generate timer interrupt clocks for a real-time operating system. The timer interrupt clocks can be generated by dividing the system clock or selecting an external input clock. As a result, the tick can be set independent of the system clock frequency. MOUSEIF (Serial Mouse Interface) The MOUSEIF functional block is used as the data receive port for a standard serial mouse. The communication parameters such as parity bit, stop bit, data bits and baud rate can be changed by software. In addition, the interrupt signal generation timing can be set to either 3-byte or 1-byte intervals. Therefore, this functional block can be used as a general-purpose receive serial port as well as the mouse serial port. Note that the mouse transmits an XY coordinate value to the serial port in 3-byte packets. MPDMAC (Micro-Programmable DMA Controller) The MPDMAC functional block is used as the DMA controller. With this controller, the operation can be programmed by a 16-instruction micro code. These instructions can be programmed to support data read operations from the LC8951 (RCHIP), data write operations to the LC8955 as well as the basic transfer operations with memory. In addition, they include rather complicated instructions to enable data comparison, logical operation and conditional jump operations. Therefore, this controller block can be used as a sub-CPU to enable intelligent processing, and to reduce the load on the MPU. BERRGEN (Bus Error Generator) The BERRGEN functional block is used to generate the bus error signal for the 68000 MPU when no AS (active low) signal is detected. There are four AS signal inactive periods. The user is allowed to select one from the four to best suit the application system in mind. CLKDIV (Clock Divider Circuit) The CLKDIV function block is used to generate the MPU clock with 1: 1 duty cycle by dividing the master clock by 2.
No.3411-8/9
LC8953
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of August, 2001. Specifications and information herein are subject to change without notice.
PS No.3411-9/9

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